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Home»Machine-Learning»Nano Labs Launches FPU3.0 ASIC Design Structure with 3D DRAM Stacking for AI and Blockchain Innovation
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Nano Labs Launches FPU3.0 ASIC Design Structure with 3D DRAM Stacking for AI and Blockchain Innovation

Editorial TeamBy Editorial TeamDecember 26, 2024Updated:December 26, 2024No Comments2 Mins Read
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Nano Labs Launches FPU3.0 ASIC Design Structure with 3D DRAM Stacking for AI and Blockchain Innovation
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Nano Labs Ltd a number one fabless built-in circuit design firm and product answer supplier in China, at the moment introduced the launch of FPU3.0, an ASIC structure designed to reinforce synthetic intelligence (AI) inference and blockchain efficiency. That includes superior 3D DRAM stacking know-how, FPU3.0 delivers a fivefold increase in energy effectivity over the earlier FPU2.0 structure, setting a brand new customary for energy-efficient, high-performance ASICs. This newest development highlights the Firm’s sturdy analysis and improvement capabilities in adopting cutting-edge applied sciences and its dedication to driving innovation and widespread adoption within the AI and cryptocurrency trade.

Additionally Learn: Trane Applied sciences to Purchase BrainBox AI

The FPU collection represents Nano Labs’ proprietary set of ASIC chip design architectures, purpose-built for high-bandwidth Excessive Throughput Computing (HTC) functions. Such ASIC chips are optimized for particular capabilities or functions, usually delivering decrease energy consumption and better computational effectivity than general-purpose CPUs and GP-GPUs. These ASICs are more and more utilized in AI inference, edge AI computing, knowledge transmission processing beneath 5G networks, community acceleration, and extra.

The Nano FPU structure contains 4 elementary modules and IPs: the Good NOC (Community-on-Chip), the high-bandwidth reminiscence controller, the chip-to-chip interconnect IOs, and the FPU core. This modular supplies outstanding flexibility, enabling fast product iteration by updating the FPU core IP whereas reusing or upgrading different IPs and modules as wanted – typically enough to introduce new options.

Notably, the FPU3.0 structure incorporates stacked 3D reminiscence with a theoretical bandwidth of 24TB/s and an upgraded Good-NOC on-chip community. This community helps a mixture of giant and small compute cores, full-crossbar, and feed-through site visitors varieties on the bus. The FPU3.0 structure holds the potentials to excel in numerous fields, delivering superior efficiency, decrease energy consumption, and sooner product iteration cycles.

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[To share your insights with us as part of editorial or sponsored content, please write to psen@itechseries.com]



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