Marvell Know-how, Inc. a frontrunner in knowledge infrastructure semiconductor options, has expanded the packaging ecosystem for AI infrastructure with an progressive multi-die resolution that lowers whole value of possession (TCO) for customized AI accelerator silicon. The superior packaging platform is a part of the Marvell™ complete IP portfolio for customized AI compute platforms—and permits multi-chip accelerator designs 2.8x bigger than standard single-die implementations. The Marvell method can allow extra environment friendly die-to-die interconnect, decrease energy consumption, elevated chiplet yields and decrease product value, and supplies a producing various to conventional interposer-based multi-chip approaches. The packaging platform has been certified with a serious hyperscaler and is now ramping in manufacturing.
Additionally Learn: Why multimodal AI is taking on communication
Within the AI period, chip packaging has turn into essential for growing compute density whereas successfully managing energy, thermal dissipation, optical I/O, sign integrity, and different components that impression the efficiency and reliability in multi-die chiplet designs. Concurrently, rising provide chain complexity and prolonged lead instances current important challenges for scaling superior packaging options. The brand new Marvell packaging resolution permits hyperscalers to beat these limitations, accelerating time-to-market whereas providing provide chain flexibility.
That is the newest innovation in a sequence of developments for purchasers of Marvell customized XPU options. This extremely optimized multi-chip packaging platform was designed from the bottom up with the not too long ago introduced Marvell customized HBM and CPO options in thoughts. Taken collectively, Marvell is constructing the business’s broadest know-how platform to allow customized XPU design for the long run.
“Superior packaging is among the main autos for advancing compute density in AI clusters and cloud,” mentioned Will Chu, senior vice chairman and common supervisor of Customized Cloud Options at Marvell. “With out it, AI infrastructure could be considerably dearer and power-hungry. We stay up for collaborating with our companions and clients to additional unlock the potential of superior packaging.”
“Chiplets represent probably the most dynamic segments of the semiconductor market. We anticipate that chiplet processor income will develop by 31% per yr to achieve $145 billion by 2030,” mentioned James Sanders, senior analyst at TechInsights. “Superior packaging applied sciences are essential to the evolution of chiplets, giving designers a framework by which to experiment.”
Interposers function the foundational layer with compute, dies, reminiscence, and different parts stacked above and speaking by means of the interposer. The Marvell re-distribution layer (RDL) presents a compelling various to conventional silicon interposers for knowledge middle functions. The Marvell method integrates 1390 mm2 of silicon and 4 items of high-bandwidth reminiscence 3/3E (HBM3/3E) reminiscence stacks and makes use of six interposer RDL layers. This permits multi-die AI accelerator options which can be 2.8 instances bigger than the biggest attainable single-chip design. The Marvell multi-die packaging resolution permits for shorter die-to-die interconnects and a modular RDL interposer.
The Marvell RDL interposer reduces design value by means of its modular design. In standard chiplets, a single interposer will span the ground area of the chips it connects effectively as any space between them. If two computing cores are on reverse sides of a chiplet bundle, the interposer will cowl your complete area. In contrast, Marvell RDL interposers are form-fitted to particular person computing dies and related by high-bandwidth paths. Not solely does this method cut back supplies, it additionally will increase chiplet yields by enabling producers to switch particular person dies.
The Marvell multi-die packaging platform permits the mixing of passive units to cut back potential sign noise inside the chiplet bundle brought on by the facility provide. In collaboration with the packaging ecosystem, Marvell has prolonged the answer to assist a number of parts inside a single bundle, enabling the mixing of probably the most complicated AI designs.
Additionally Learn: AiThority Interview with Nicole Janssen, Co-Founder and Co-CEO of AltaML
As well as, hyperscalers can now make use of the packaging know-how to construct XPUs with HBM3 and HBM3E reminiscence and Marvell is actively qualifying the know-how for future HBM4 designs.
Ecosystem Quotes
“Modern packaging applied sciences are essential to the adoption of chiplet architectures in present and future generations of AI and accelerated compute units,” mentioned Dr. Mike Hung, senior vice chairman at Superior Semiconductor Engineering (ASE). “Our shut collaboration with Marvell permits us to develop options that ship larger ranges of efficiency and effectivity, whereas reaching a broader viewers throughout the design ecosystem.”
“2.5D packaging know-how continues to modernize heterogeneous IC packaging, enabling high-performance, cost-effective integration of a number of chiplet and reminiscence modules,” mentioned Kevin Engel, chief working officer at Amkor Know-how. “This know-how not solely will increase I/O and circuit density, but in addition paves the way in which for superior 3D constructions, making it indispensable for the subsequent era of functions.”
“Probably the most difficult difficulty within the AI/ML resolution design is to create an efficient energy supply community, as GPUs are more and more utilizing extra energy. SEMCO is proud to have collaborated with Marvell to create a number one energy supply resolution utilizing its customized silicon capacitors and passive parts,” mentioned Taegon Lee, govt vice chairman and head of the Strategic Advertising and marketing Heart at Samsung Electro-Mechanics (SEMCO). “The ecosystem method we collectively took in creating this resolution will quickly turn into the norm. We stay up for continued collaboration with Marvell.”
“RDL-based chiplet integration offers Marvell the flexibleness to decide on the optimum course of know-how for every a part of their design,” mentioned CB Chang, president and CEO at Siliconware USA, Inc., a subsidiary of SPIL. “Because the business continues to maneuver towards chiplet-based architectures, this flexibility permits extra complicated and environment friendly system integration.”
Marvell Customized Technique
The Marvell customized platform technique seeks to ship breakthrough outcomes by means of distinctive semiconductor designs and progressive approaches. By combining experience in system and semiconductor design, superior course of manufacturing, and a complete portfolio of semiconductor platform options and IP—together with electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D units, silicon photonics, co-packaged copper, customized HBM, system-on-chip (SoC) materials, optical IO, and compute cloth interfaces resembling PCIe Gen 7— Marvell is ready to create platforms in collaboration with clients that rework infrastructure efficiency, effectivity and worth.
[To share your insights with us, please write to psen@itechseries.com]
